例句與用法

1. According to elaborate analysis of clock logic in general purpose processor , we apply multi - bit clock gated flip - flops design to reduce the power of registers and clock trees concurrently , so the power of the clock network in processors can be drastically reduced . 3 . a low power issue queue architecture is proposed
   一方面利用帶門控使能的觸發(fā)器電路降低時鐘節(jié)點的平均翻轉(zhuǎn),另一方面通過多比特觸發(fā)器的采用進(jìn)一步降低了時鐘樹規(guī)模,從而在不增加asic物理設(shè)計復(fù)雜度的情況下大大降低了龍芯處理器的時鐘網(wǎng)絡(luò)功耗; 3 .提出了亂序多發(fā)射隊列的低功耗結(jié)構(gòu)。